a) Field of the Invention
The present invention relates to a memory device, and more particularly to a memory device operating as static random access memories.
b) Description of the Related Art
An SRAM memory cell has two stable points and maintains the same state at each stable point while power is supplied to the cell.
An SRAM cell using metal oxide semiconductor (MOS) transistors includes basically two driver transistors and two loads. Each load is made of a MOS transistor or resistor.
Two sets of serial circuits each having a driver transistor and a load are connected in parallel. An interconnection node of each serial circuit is connected to the gate of the driver transistor of the other serial circuit. This circuit, like a flip-flop, takes two stable states by turning on one driver transistor and turning off the other driver transistor.
There has been a strong demand for increasing the memory capacity of SRAM devices as well as other semiconductor integrated circuits. The memory capacity can be increased by raising the integration degree of MOS transistors constituting memory cells through miniaturization thereof or through other means. However, increasing the capacity of a memory constituted by SRAM cells of the type using four driver transistors is limited more than dynamic random access memory (DRAM) cells each using one transistor and one capacitor.
A memory cell using a negative differential resistance element has drawn much attention as a memory structure able to form an SRAM with a more simplified structure. If an appropriate load is serially connected to a negative differential resistance element, three stable operating points can be obtained. Of the three stable operating points, an SRAM cell can be realized by using two outermost stable points.
As a negative differential resistance element, there is known an Esaki diode which uses the tunneling phenomenon at a high impurity concentration p.sup.+ n.sup.+ junction. Recently, a resonance tunnel diode (RTD) having a quantum well structure has been developed in which a semiconductor layer (quantum well layer) such as GaAs having a relatively narrow band gap is sandwiched between semiconductor layers (potential barrier layers) such as GaAlAs having a relatively wide band gap.
As the thickness of the quantum well layer between the potential barrier layers is made small, the band is transformed into levels because of one-dimensional quantization. If the energy of externally supplied charge carriers matches one of the levels, current flows, and if the energy mismatches the level, the current reduces. If the energy of charge carriers again matches the next level, the current increases again.
FIG. 12 shows an SRAM memory circuit using RTDs according to a conventional technique. A plurality of word lines WL are arranged in the horizontal direction as viewed in FIG. 12, whereas a plurality of bit lines BL are arranged the vertical direction, to form a matrix configuration.
A memory cell 10 is connected at each cross point of the matrix. Each memory cell 10 has a driver diode DR, a load diode LD, and a transfer gate TG.
The driver diode DR and load diode LD are each formed by a resonance tunnel diode (RTD), and serially connected between a power supply voltage V.sub.dd and a ground potential (GND).
The transfer gate TG is formed, for example, by a high electron mobility transistor (HEMT) whose pair of current terminals are connected between a bit line BL and an interconnection node between the driver diode DR and load diode LD, and whose control terminal is connected to the word line WL.
Each word line WL is driven by an X selector 2. Each bit line BL is connected to a column sense circuit (CS) 5, and via a transfer gate M to a data input circuit 4. The gate of the transfer gate M is driven by an output of an AND gate (AND).
Two inputs of the AND gate are supplied to a write controller 3 and a Y selector 6. An output of the Y selector 6 is also supplied to the column sense circuit 5. An output of each column sense circuit 5 is supplied via a common data line DL to a main sense (MS) circuit 7.
In writing data to a memory cell, an AND gate is selected by the write controller 3 and Y selector 6 to turn on a particular transfer gate M and supply data to the corresponding bit line BL from the data input circuit 4.
The X selector 2 selects a particular word line WL to turn on the transfer gate TG connected to the selected word line WL. In this manner, the data is written to the memory cell 10 connected to the bit line BL to which the data was supplied and to the word line WL selected by a select signal.
In reading data, a particular memory cell 10 is selected by the X selector 2 and Y selector 6. Data read from the selected memory cell 10 via the turned-on transfer gate is transferred via the bit line BL to the column sense circuit 5 and sensed by the main sense circuit 7.
One end of each bit line BL opposite to the transfer gate M is connected to a pull-up resistor R which is connected to the power supply voltage V.sub.dd. An RTD can realize a memory cell of a low power consumption operating at a low power, but has a small capability of charging/discharging the bit line during the data read. The pull-up resistor R has a function of increasing the current supply ability when a memory cell is selected.
FIG. 13 illustrates the fundamental characteristics of the memory circuit shown in FIG. 12. The abscissa represents a voltage V in units of volt, and the ordinate represents a current I in units of .mu.A. A curve "a" indicates the characteristic of a driver diode DR. A curve "b" indicates a load characteristic of a load diode LD. A curve "c" indicates a load characteristic of a pull-up resistor R relative to the driver diode DR when the transfer gate DR turns on.
When a transfer gate TG turns on and a memory cell is selected, both the load diode LD and pull-up resistor R serve as the load of the driver diode DR. A curve "d" indicates the total load characteristic of the characteristics c and "b" of the pull-up resistor R and load diode LD.
The negative differential resistance characteristics shown in FIG. 13 are approximated by broken lines as shown in FIG. 14. Reference symbols for broken lines in FIG. 14 correspond to those shown in FIG. 13.
Under the condition that any memory cell is not selected, each driver diode DR is connected only to its load diode LD. Under this condition, the load characteristic of the driver diode DR is represented by the load characteristic b of the load diode so that intersecting points A.sub.0 and B.sub.0 become the stable operating points of the memory cell.
When a transfer gate TG turns on and a memory cell is selected, the load characteristic changes to the characteristic "d" and the stable points of the memory cell change to X and Y. Namely, in reading/writing data, the bit line BL is charged/discharged at the potential of X or Y.
As compared to the stable points A.sub.0 and B.sub.0 without the pull-up resistor, the current values with the pull-up resistor increase at the stable points X and Y. The shift of the high potential side stable points from B.sub.0 to Y is less than that of the low potential side stable 2points from A.sub.0 to X, so that the potential difference between "1" and "0" states becomes small.
The shift from the stable points A.sub.0 and B.sub.0 at the non-select state of a memory cell to the stable points X and Y at the select state of a memory cell is continuously and stably performed on the operating characteristic curve "a" of the driver diode. Similarly, when the memory cell select state transits to the memory cell non-select state, the stable points X and Y continuously and stably shift to the stable points A.sub.0 and B.sub.0 of the memory cell non-select state.
As described above, addition of a pull-up resistor to a bit line ensures the following advantages:
(1) providing stable high and low levels at the memory cell select state;
(2) suppressing the amplitude of a change in potential between the memory cell non-select state and select state, speeding up the operation;
(3) allowing current to flow as much as possible within a total power consumption limit, speeding up the operation; and
(4) preventing the memory cell information from being destroyed when selecting a memory cell.
If a pull-up resistor is used as a bit line pull-up circuit in the memory circuit using negative differential resistor elements shown in FIG. 12, this pull-up resistor is required to be formed by a process different from the processes of forming other memory constituent elements.
A different process makes it difficult to precisely control the characteristics of a pull-up resistor. For example, the cases such as shown in FIGS. 15A and 15B may occur depending upon a change in process parameters.
In the case of FIG. 15A, the resistance value of a pull-up resistor is smaller than a designed value and the load characteristic "c" becomes so steep that the total load characteristic curve "d" intersects the operating characteristic curve "a" of the driver diode only at one point.
The peak of the driver diode characteristic curve "a" goes away from the valley of the load characteristic curve "d", caving only the stable point Y at the memory cell select-state. Therefore, the contents of the memory cell are destroyed.
In the case of FIG. 15B, the valley of the total load characteristic curve "d" of the load diode LD and pull-up resistor R contacts the peak of the operating characteristic curve "a" of the driver diode DR. Depending upon the process parameters, the load characteristic curve d contacts or does not contact the driver diode characteristic curve "a", making the characteristic of the memory cell unstable.
The amount of current at the low potential side stable point becomes greater than that at the high potential side stable points, by the effects of the total load characteristic. If the current amount at the high potential side, stable points is to be made high, it is necessary to make the slope of the total load characteristic curve steep. In this case, as shown in FIG. 15A, the load characteristic curve may depart from the driver diode characteristic curve.